 |
AIROC™ BTSDK v4.6 - Documentation | |||
|
AIROC™ BTSDK v4.6 - Documentation | |||
Define functions to access Spiffy driver. More...
Data Structures | |
| struct | SpiffyState |
Typedefs | |
| typedef enum SpiffyInstance | SpiffyInstance |
| Defines a spiffy driver class. More... | |
|
typedef enum Spi1MasterGpioConfigType | Spi1MasterGpioConfigType |
| Available conbination for SPI 1 support. | |
|
typedef enum Spi2MasterGpioConfigType | Spi2MasterGpioConfigType |
| All the available GPIO combinations for SPI-2 Master mode. | |
|
typedef enum Spi2SlaveGpioConfigType | Spi2SlaveGpioConfigType |
| All the available GPIO combinations for SPI-2 SLAVE mode. | |
| typedef enum SPI_ENDIAN | SPI_ENDIAN |
| Type Definitions. | |
| typedef enum SPI_SS_MODE | SPI_SS_MODE |
| Slave Select mode (output from master) | |
| typedef enum SPI_SS_POLARITY | SPI_SS_POLARITY |
| Slave select polarity (output from master) | |
| typedef enum SPI_MODE | SPI_MODE |
| Clock polarity and phase If CPOL=0, base value of the clock is zero If CPOL=1, base value of the clock is one If CPHA=0, sample on leading (first) clock edge If CPHA=1, sample on trailing (second) clock edge. | |
Enumerations | |
| enum | SpiffyInstance { SPIFFYD_1 = 0, SPIFFYD_2 = 1, MAX_SPIFFYS = 2 } |
| Defines a spiffy driver class. More... | |
| enum | Spi1MasterGpioConfigType { MASTER1_P24_MISO = (int)0xe0e1e218, MASTER1_P26_MISO = (int)0xe0e1e21a, MASTER1_P32_MISO = (int)0xe0e1e220, MASTER1_P39_MISO = (int)0xe0e1e227 } |
| Available conbination for SPI 1 support. | |
| enum | Spi2MasterGpioConfigType { MASTER2_P03_CLK_P00_MOSI_P01_MISO = 0x00030001, MASTER2_P03_CLK_P00_MOSI_P05_MISO = 0x00030005, MASTER2_P03_CLK_P02_MOSI_P01_MISO = 0x00030201, MASTER2_P03_CLK_P02_MOSI_P05_MISO = 0x00030205, MASTER2_P03_CLK_P04_MOSI_P01_MISO = 0x00030401, MASTER2_P03_CLK_P04_MOSI_P05_MISO = 0x00030405, MASTER2_P03_CLK_P27_MOSI_P01_MISO = 0x00031b01, MASTER2_P03_CLK_P27_MOSI_P05_MISO = 0x00031b05, MASTER2_P03_CLK_P38_MOSI_P01_MISO = 0x00032601, MASTER2_P03_CLK_P38_MOSI_P05_MISO = 0x00032605, MASTER2_P07_CLK_P00_MOSI_P01_MISO = 0x00070001, MASTER2_P07_CLK_P00_MOSI_P05_MISO = 0x00070005, MASTER2_P07_CLK_P02_MOSI_P01_MISO = 0x00070201, MASTER2_P07_CLK_P02_MOSI_P05_MISO = 0x00070205, MASTER2_P07_CLK_P04_MOSI_P01_MISO = 0x00070401, MASTER2_P07_CLK_P04_MOSI_P05_MISO = 0x00070405, MASTER2_P07_CLK_P27_MOSI_P01_MISO = 0x00071b01, MASTER2_P07_CLK_P27_MOSI_P05_MISO = 0x00071b05, MASTER2_P07_CLK_P38_MOSI_P01_MISO = 0x00072601, MASTER2_P07_CLK_P38_MOSI_P05_MISO = 0x00072605, MASTER2_P24_CLK_P00_MOSI_P25_MISO = 0x00180019, MASTER2_P24_CLK_P02_MOSI_P25_MISO = 0x00180219, MASTER2_P24_CLK_P04_MOSI_P25_MISO = 0x00180419, MASTER2_P24_CLK_P27_MOSI_P25_MISO = 0x00181b19, MASTER2_P24_CLK_P38_MOSI_P25_MISO = 0x00182619, MASTER2_P36_CLK_P00_MOSI_P25_MISO = 0x00240019, MASTER2_P36_CLK_P02_MOSI_P25_MISO = 0x00240219, MASTER2_P36_CLK_P04_MOSI_P25_MISO = 0x00240419, MASTER2_P36_CLK_P27_MOSI_P25_MISO = 0x00241b19, MASTER2_P36_CLK_P38_MOSI_P25_MISO = 0x00242619 } |
| All the available GPIO combinations for SPI-2 Master mode. | |
| enum | Spi2SlaveGpioConfigType { SLAVE2_P02_CS_P03_CLK_P00_MOSI_P01_MISO = 0x02030001, SLAVE2_P02_CS_P03_CLK_P00_MOSI_P05_MISO = 0x02030005, SLAVE2_P02_CS_P03_CLK_P00_MOSI_P25_MISO = 0x02030019, SLAVE2_P02_CS_P03_CLK_P04_MOSI_P01_MISO = 0x02030401, SLAVE2_P02_CS_P03_CLK_P04_MOSI_P05_MISO = 0x02030405, SLAVE2_P02_CS_P03_CLK_P04_MOSI_P25_MISO = 0x02030419, SLAVE2_P02_CS_P07_CLK_P00_MOSI_P01_MISO = 0x02070001, SLAVE2_P02_CS_P07_CLK_P00_MOSI_P05_MISO = 0x02070005, SLAVE2_P02_CS_P07_CLK_P00_MOSI_P25_MISO = 0x02070019, SLAVE2_P02_CS_P07_CLK_P04_MOSI_P01_MISO = 0x02070401, SLAVE2_P02_CS_P07_CLK_P04_MOSI_P05_MISO = 0x02070405, SLAVE2_P02_CS_P07_CLK_P04_MOSI_P25_MISO = 0x02070419, SLAVE2_P06_CS_P03_CLK_P00_MOSI_P01_MISO = 0x06030001, SLAVE2_P06_CS_P03_CLK_P00_MOSI_P05_MISO = 0x06030005, SLAVE2_P06_CS_P03_CLK_P00_MOSI_P25_MISO = 0x06030019, SLAVE2_P06_CS_P03_CLK_P04_MOSI_P01_MISO = 0x06030401, SLAVE2_P06_CS_P03_CLK_P04_MOSI_P05_MISO = 0x06030405, SLAVE2_P06_CS_P03_CLK_P04_MOSI_P25_MISO = 0x06030419, SLAVE2_P06_CS_P07_CLK_P00_MOSI_P01_MISO = 0x06070001, SLAVE2_P06_CS_P07_CLK_P00_MOSI_P05_MISO = 0x06070005, SLAVE2_P06_CS_P07_CLK_P00_MOSI_P25_MISO = 0x06070019, SLAVE2_P06_CS_P07_CLK_P04_MOSI_P01_MISO = 0x06070401, SLAVE2_P06_CS_P07_CLK_P04_MOSI_P05_MISO = 0x06070405, SLAVE2_P06_CS_P07_CLK_P04_MOSI_P25_MISO = 0x06070419, SLAVE2_P26_CS_P24_CLK_P27_MOSI_P01_MISO = 0x1a181b01, SLAVE2_P26_CS_P24_CLK_P27_MOSI_P05_MISO = 0x1a181b05, SLAVE2_P26_CS_P24_CLK_P27_MOSI_P25_MISO = 0x1a181b19, SLAVE2_P26_CS_P24_CLK_P33_MOSI_P01_MISO = 0x1a182101, SLAVE2_P26_CS_P24_CLK_P33_MOSI_P05_MISO = 0x1a182105, SLAVE2_P26_CS_P24_CLK_P33_MOSI_P25_MISO = 0x1a182119, SLAVE2_P26_CS_P24_CLK_P38_MOSI_P01_MISO = 0x1a182601, SLAVE2_P26_CS_P24_CLK_P38_MOSI_P05_MISO = 0x1a182605, SLAVE2_P26_CS_P24_CLK_P38_MOSI_P25_MISO = 0x1a182619, SLAVE2_P26_CS_P36_CLK_P27_MOSI_P01_MISO = 0x1a241b01, SLAVE2_P26_CS_P36_CLK_P27_MOSI_P05_MISO = 0x1a241b05, SLAVE2_P26_CS_P36_CLK_P27_MOSI_P25_MISO = 0x1a241b19, SLAVE2_P26_CS_P36_CLK_P33_MOSI_P01_MISO = 0x1a242101, SLAVE2_P26_CS_P36_CLK_P33_MOSI_P05_MISO = 0x1a242105, SLAVE2_P26_CS_P36_CLK_P33_MOSI_P25_MISO = 0x1a242119, SLAVE2_P26_CS_P36_CLK_P38_MOSI_P01_MISO = 0x1a242601, SLAVE2_P26_CS_P36_CLK_P38_MOSI_P05_MISO = 0x1a242605, SLAVE2_P26_CS_P36_CLK_P38_MOSI_P25_MISO = 0x1a242619, SLAVE2_P32_CS_P24_CLK_P27_MOSI_P01_MISO = 0x20181b01, SLAVE2_P32_CS_P24_CLK_P27_MOSI_P05_MISO = 0x20181b05, SLAVE2_P32_CS_P24_CLK_P27_MOSI_P25_MISO = 0x20181b19, SLAVE2_P32_CS_P24_CLK_P33_MOSI_P01_MISO = 0x20182101, SLAVE2_P32_CS_P24_CLK_P33_MOSI_P05_MISO = 0x20182105, SLAVE2_P32_CS_P24_CLK_P33_MOSI_P25_MISO = 0x20182119, SLAVE2_P32_CS_P24_CLK_P38_MOSI_P01_MISO = 0x20182601, SLAVE2_P32_CS_P24_CLK_P38_MOSI_P05_MISO = 0x20182605, SLAVE2_P32_CS_P24_CLK_P38_MOSI_P25_MISO = 0x20182619, SLAVE2_P32_CS_P36_CLK_P27_MOSI_P01_MISO = 0x20241b01, SLAVE2_P32_CS_P36_CLK_P27_MOSI_P05_MISO = 0x20241b05, SLAVE2_P32_CS_P36_CLK_P27_MOSI_P25_MISO = 0x20241b19, SLAVE2_P32_CS_P36_CLK_P33_MOSI_P01_MISO = 0x20242101, SLAVE2_P32_CS_P36_CLK_P33_MOSI_P05_MISO = 0x20242105, SLAVE2_P32_CS_P36_CLK_P33_MOSI_P25_MISO = 0x20242119, SLAVE2_P32_CS_P36_CLK_P38_MOSI_P01_MISO = 0x20242601, SLAVE2_P32_CS_P36_CLK_P38_MOSI_P05_MISO = 0x20242605, SLAVE2_P32_CS_P36_CLK_P38_MOSI_P25_MISO = 0x20242619, SLAVE2_P39_CS_P24_CLK_P27_MOSI_P01_MISO = 0x27181b01, SLAVE2_P39_CS_P24_CLK_P27_MOSI_P05_MISO = 0x27181b05, SLAVE2_P39_CS_P24_CLK_P27_MOSI_P25_MISO = 0x27181b19, SLAVE2_P39_CS_P24_CLK_P33_MOSI_P01_MISO = 0x27182101, SLAVE2_P39_CS_P24_CLK_P33_MOSI_P05_MISO = 0x27182105, SLAVE2_P39_CS_P24_CLK_P33_MOSI_P25_MISO = 0x27182119, SLAVE2_P39_CS_P24_CLK_P38_MOSI_P01_MISO = 0x27182601, SLAVE2_P39_CS_P24_CLK_P38_MOSI_P05_MISO = 0x27182605, SLAVE2_P39_CS_P24_CLK_P38_MOSI_P25_MISO = 0x27182619, SLAVE2_P39_CS_P36_CLK_P27_MOSI_P01_MISO = 0x27241b01, SLAVE2_P39_CS_P36_CLK_P27_MOSI_P05_MISO = 0x27241b05, SLAVE2_P39_CS_P36_CLK_P27_MOSI_P25_MISO = 0x27241b19, SLAVE2_P39_CS_P36_CLK_P33_MOSI_P01_MISO = 0x27242101, SLAVE2_P39_CS_P36_CLK_P33_MOSI_P05_MISO = 0x27242105, SLAVE2_P39_CS_P36_CLK_P33_MOSI_P25_MISO = 0x27242119, SLAVE2_P39_CS_P36_CLK_P38_MOSI_P01_MISO = 0x27242601, SLAVE2_P39_CS_P36_CLK_P38_MOSI_P05_MISO = 0x27242605, SLAVE2_P39_CS_P36_CLK_P38_MOSI_P25_MISO = 0x27242619 } |
| All the available GPIO combinations for SPI-2 SLAVE mode. | |
| enum | { MASTER2_CONFIG = 1, SLAVE2_CONFIG = 2 } |
| enum | SPI_ENDIAN { SPI_MSB_FIRST, SPI_LSB_FIRST } |
| Type Definitions. More... | |
| enum | SPI_SS_MODE { SPI_SS_NORMAL, SPI_SS_INACTIVE_BTW_BYTES } |
| Slave Select mode (output from master) More... | |
| enum | SPI_SS_POLARITY { SPI_SS_ACTIVE_LOW, SPI_SS_ACTIVE_HIGH } |
| Slave select polarity (output from master) More... | |
| enum | SPI_MODE { SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3 } |
| Clock polarity and phase If CPOL=0, base value of the clock is zero If CPOL=1, base value of the clock is one If CPHA=0, sample on leading (first) clock edge If CPHA=1, sample on trailing (second) clock edge. More... | |
| enum | { INPUT_PIN_PULL_UP = 0x0400, INPUT_PIN_PULL_DOWN = 0x0200, INPUT_PIN_FLOATING = 0x0 } |
| enum | { SPIFFYD_CS_SHIFT = 24, SPIFFYD_CLK_SHIFT = 16, SPIFFYD_MOSI_SHIFT = 8, SPIFFYD_MISO_SHIFT = 0, SPIFFYD_PIN_MASK = 0xff } |
| enum | { SPIFFYD_BIT_11 = (1<<11), SPIFFYD_BIT_10 = (1<<10), SPIFFYD_BIT_8 = (1<<8), SPIFFYD_BIT_7 = (1<<7), SPIFFYD_BIT_6 = (1<<6), SPIFFYD_BIT_5 = (1<<5), SPIFFYD_BIT_4 = (1<<4), SPIFFYD_BIT_3 = (1<<3), SPIFFYD_BIT_2 = (1<<2), SPIFFYD_BIT_0 = (1<<0), MASTER_2_CLOCK_IOPREMUX_MASK = ((SPIFFYD_BIT_8) | (SPIFFYD_BIT_11)), MASTER_2_MISO_IOPREMUX_MASK = SPIFFYD_BIT_10, SLAVE_2_CLOCK_IOPREMUX_MASK = ((SPIFFYD_BIT_8) | (SPIFFYD_BIT_11)), MASTER1_MISO_IOPREMUX_MASK = (SPIFFYD_BIT_7 | SPIFFYD_BIT_6), SLAVE_2_MOSI_IOPREMUX_MASK = (SPIFFYD_BIT_4 | SPIFFYD_BIT_5), SLAVE_2_CS_IOPREMUX_MASK = (SPIFFYD_BIT_3 | SPIFFYD_BIT_2), IOCFG_PREMUX_MISO_ROUTING_P5 = SPIFFYD_BIT_10, IOCFG_PREMUX_CS_ROUTING_P2 = 0, IOCFG_PREMUX_CS_ROUTING_P6 = SPIFFYD_BIT_2, IOCFG_PREMUX_CS_ROUTING_P26 = 0, IOCFG_PREMUX_CS_ROUTING_P32 = SPIFFYD_BIT_2, IOCFG_PREMUX_CS_ROUTING_P39 = SPIFFYD_BIT_3, IOCFG_PREMUX_MISO_ROUTING_P24 = 0, IOCFG_PREMUX_MISO_ROUTING_P26 = SPIFFYD_BIT_6, IOCFG_PREMUX_MISO_ROUTING_P32 = SPIFFYD_BIT_7, IOCFG_PREMUX_MISO_ROUTING_P39 = (SPIFFYD_BIT_6|SPIFFYD_BIT_7), IOCFG_PREMUX_CLK_ROUTING_P7 = (SPIFFYD_BIT_8 | SPIFFYD_BIT_11), IOCFG_PREMUX_CLK_ROUTING_P3 = SPIFFYD_BIT_11, IOCFG_PREMUX_CLK_ROUTING_P36 = SPIFFYD_BIT_8, IOCFG_PREMUX_CLK_ROUTING_P24 = 0, IOCFG_PREMUX_MOSI_ROUTING_P0 = 0, IOCFG_PREMUX_MOSI_ROUTING_P4 = SPIFFYD_BIT_4, IOCFG_PREMUX_MOSI_ROUTING_P27 = 0, IOCFG_PREMUX_MOSI_ROUTING_P33 = SPIFFYD_BIT_4, IOCFG_PREMUX_MOSI_ROUTING_P38 = SPIFFYD_BIT_5 } |
| enum | { OUTPUT_FN_SEL_3 = 0x30, OUTPUT_FN_SEL_2 = 0x20, MAIN60HZ_SPI_MASK = (SPIFFYD_BIT_3 | SPIFFYD_BIT_4), MAIN60HZ_SPI_MISO_P27 = SPIFFYD_BIT_4, MAIN60HZ_SPI_MISO_P2 = SPIFFYD_BIT_4, MAIN60HZ_SPI_MISO_P24 = SPIFFYD_BIT_4, CR_PAD_FCN_CTL2_RXD_MASK = 0x0300, CR_PAD_FCN_CTL2_RXD_SHIFT = 8 } |
Functions | |
| void | spiffyd_init (SpiffyInstance instance) |
| Initializes the instance of the SPIFFY driver. More... | |
| void | spiffyd_configure (SpiffyInstance instance, UINT32 clkSpeedInHz, SPI_ENDIAN endian, SPI_SS_POLARITY polarity, SPI_MODE mode) |
| Set up the spiffy hardware block configuration. More... | |
| void | spiffyd_reset (SpiffyInstance instance) |
| Reset and bring the spiffy driver to a known good state with default configuration. More... | |
| void | spiffyd_active (SpiffyInstance instance) |
| Reapply any gpio configuration necessary for spiffy operation. More... | |
| void | spiffyd_idle (SpiffyInstance instance) |
| Set the gpios used for clk, mosi, and miso to general purpose gpios to prevent any glitches from causing invalid bits to get clocked in. More... | |
| void | spiffyd_txByte (SpiffyInstance instance, UINT8 b) |
| Transmit one 8-bit value. More... | |
| void | spiffyd_txHalfWord (SpiffyInstance instance, UINT16 h) |
| Transmit one 16-bit value as two bytes, least significant byte first. More... | |
| void | spiffyd_txWord (SpiffyInstance instance, UINT32 w) |
| Transmit one 32-bit value as four bytes, least significant byte first. More... | |
| void | spiffyd_txData (SpiffyInstance instance, UINT32 txLen, const UINT8 *txBuf) |
| Transmit one buffer of data. More... | |
| void | spiffyd_exchangeData (SpiffyInstance instance, UINT32 len, const UINT8 *txBuf, UINT8 *rxBuf) |
| Transmit one buffer of data while simultaneously receiving data. More... | |
| void | spiffyd_rxData (SpiffyInstance instance, UINT32 rxLen, UINT8 *rxBuf) |
| Receive data into the buffer. More... | |
| void | spiffyd_slaveEnableTx (SpiffyInstance instance) |
| Enable the tx fifo so any data in it will be transmitted when the SPI master clocks it out. More... | |
| void | spiffyd_slaveDisableTx (SpiffyInstance instance) |
| Disable the tx fifo. More... | |
| void | spiffyd_slaveEnableRx (SpiffyInstance instance) |
| Enable the rx fifo so data will be received into it when the SPI master clocks it in. More... | |
| void | spiffyd_slaveDisableRx (SpiffyInstance instance) |
| Disable the rx fifo. More... | |
| void | spiffyd_slaveTxData (SpiffyInstance instance, UINT32 txLen, const UINT8 *txBuf) |
| Write data in the transmit buffer to the tx fifo. More... | |
| void | spiffyd_slaveTxByte (SpiffyInstance instance, UINT8 b) |
| Write one 8-bit value to the tx fifo. More... | |
| void | spiffyd_slaveTxHalfWord (SpiffyInstance instance, UINT16 h) |
| Write one 16-bit value as two bytes to the tx fifo, least significant byte first. More... | |
| void | spiffyd_slaveTxWord (SpiffyInstance instance, UINT32 w) |
| Write one 32-bit value as four bytes to the tx fifo, least significant byte first. More... | |
| UINT32 | spiffyd_slaveGetTxFifoCount (SpiffyInstance instance) |
| Get the count of bytes in the tx fifo. More... | |
| SPIFFY_STATUS | spiffyd_slaveRxData (SpiffyInstance instance, UINT32 rxLen, UINT8 *rxBuf) |
| Pull data from the rx fifo if there are at least rxLen bytes in rx fifo. More... | |
| UINT32 | spiffyd_slaveGetRxFifoCount (SpiffyInstance instance) |
| Get the count of bytes in the rx fifo. More... | |
| void | spiffyd_master1GpioConfig (Spi1MasterGpioConfigType gpioConfig) |
| Configure SPIFFY-1 Master. Internal. | |
| void | spiffyd_master2GpioConfig (Spi2MasterGpioConfigType gpioConfig) |
| Configure SPIFFY-2 Master. Internal. | |
| void | spiffyd_slave2GpioConfig (Spi2SlaveGpioConfigType gpioConfig) |
| Configure SPIFFY2 Slave. Internal. | |
| void | spiffyd_master2ConfigClk (UINT8 clkPin) |
| Configure SPIFFY2 master CLK. Internal. | |
| void | spiffyd_master2ConfigMosi (UINT8 mosiPin) |
| Configure SPIFFY2 master MOSI. Internal. | |
| void | spiffyd_master2ConfigMiso (UINT8 misoPin) |
| Configure SPIFFY2 master MISO. Internal. | |
| void | spiffyd_slave2ConfigClk (UINT8 clkPin) |
| Configure SPIFFY2 slave CLK. Internal. | |
| void | spiffyd_slave2ConfigMosi (UINT8 mosiPin) |
| Configure SPIFFY2 slave MOSI. Internal. | |
| void | spiffyd_slave2ConfigMiso (UINT8 misoPin) |
| Configure SPIFFY2 Slave MISO. Internal. | |
| void | spiffyd_slave2ConfigCs (UINT8 csPin) |
| Configure SPIFFY2 Slave CS. Internal. | |
| INLINE UINT8 | spiffyd_getGpioPort (UINT8 spiPin) |
| Convert P0-P57 to internal Port/Pin style. More... | |
| INLINE UINT8 | spiffyd_getGpioPin (UINT8 spiPin) |
| Convert P0-P57 to internal Port/Pin style. More... | |
| INLINE tSPIFFY_BLOCK * | spiffyd_getSpiffyBlkPtr (SpiffyInstance instance) |
| Given a spiffy instance, returns the spiffy control block. More... | |
Define functions to access Spiffy driver.
