Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
Macros | |
#define | CYBSP_DEBUG_UART_RX CYBSP_BT_UART_RX |
Pin: UART RX. | |
#define | CYBSP_DEBUG_UART_TX CYBSP_BT_UART_TX |
Pin: UART TX. | |
#define | CYBSP_I2C_SCL (P4_0) |
Pin: I2C SCL. | |
#define | CYBSP_I2C_SDA (P4_1) |
Pin: I2C SDA. | |
#define | CYBSP_SWDIO (P1_2) |
Pin: SWDIO. | |
#define | CYBSP_SWDCK (P1_3) |
Pin: SWDCK. | |
#define | CYBSP_SPI_MOSI CYBSP_SWDIO |
Pin: SPI MOSI. | |
#define | CYBSP_SPI_MISO CYBSP_SWDCK |
Pin: SPI MISO. | |
#define | CYBSP_SPI_CLK CYBSP_USER_LED1 |
Pin: SPI CLK. | |
#define | CYBSP_SPI_CS CYBSP_USER_BTN2 |
Pin: SPI CS. | |
#define | CYBSP_QSPI_SS (P2_0) |
Pin: QUAD SPI SS. | |
#define | CYBSP_QSPI_D3 (P2_1) |
Pin: QUAD SPI D3. | |
#define | CYBSP_QSPI_D2 (P2_2) |
Pin: QUAD SPI D2. | |
#define | CYBSP_QSPI_D1 (P2_3) |
Pin: QUAD SPI D1. | |
#define | CYBSP_QSPI_D0 (P2_4) |
Pin: QUAD SPI D0. | |
#define | CYBSP_QSPI_SCK (P2_5) |
Pin: QUAD SPI SCK. | |
#define | CYBSP_BT_UART_RX (P3_2) |
Pin: BT UART RX. | |
#define | CYBSP_BT_UART_TX (P3_3) |
Pin: BT UART TX. | |
#define | CYBSP_BT_UART_RTS (P3_1) |
Pin: BT UART RTS. | |
#define | CYBSP_BT_UART_CTS (P3_0) |
Pin: BT UART CTS. | |
#define | CYBSP_PDM_CLK (P0_0) |
Pin: PDM PCM CLK. | |
#define | CYBSP_PDM_DATA (P0_1) |
Pin PDM PCM DATA. | |
#define | CYBSP_I2S_MCLK (P0_4) |
Pin: I2S MCLK. | |
#define | CYBSP_DEBUG_UART_RTS CYBSP_BT_UART_RTS |
Pin: UART RX. | |
#define | CYBSP_DEBUG_UART_CTS CYBSP_BT_UART_CTS |
Pin: UART TX. | |