Clock paths are a series of multiplexers that allow a source clock to drive multiple clocking resources down the chain.
These paths are used for active domain clocks that are not operational during chip Deep Sleep, hibernate and off modes. Illustrated below is a diagram of the clock paths for the PSoC 63 series, showing the first three clock paths. The source clocks for these paths are highlighted in the red box.
Some clock paths such as path 0 and path 1 have additional resources that can be utilized to provide a higher frequency clock. For example, path 0 source clock can be used as the reference clock for the FLL and path 1 source clock can be used as the reference clock for the PLL.
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