GPIO (General Purpose Input Output)

General Description

The GPIO driver provides an API to configure and access device Input/Output pins.

The functions and other declarations used in this driver are in cy_gpio.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and their variants.

Initialization can be performed either at the port level or by configuring the individual pins. For efficient use of code space, port configuration should be used in the field. Refer to the product device header files for the list of supported ports and pins.

• Single pin configuration is performed by using Cy_GPIO_Pin_FastInit (provide specific values) or Cy_GPIO_Pin_Init (provide a filled cy_stc_gpio_pin_config_t structure).
• An entire port can be configured using Cy_GPIO_Port_Init. Provide a filled cy_stc_gpio_prt_config_t structure. The values in the structure are bitfields representing the desired value for each pin in the port.
• Pin configuration and management is based on the port address and pin number. Cy_GPIO_PortToAddr function can optionally be used to calculate the port address from the port number at run-time.

Once the pin/port initialization is complete, each pin can be accessed by specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API functions.

Configuration Considerations

1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection. This allows the pin to connect to signal sources/sinks throughout the device, as defined by the pin HSIOM selection options (en_hsiom_sel_t).
2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW control digital pin only) at Power-On-Reset(POR).
3. Some API functions perform read-modify-write operations on shared port registers. These functions are not thread safe and care must be taken when called by the application.
4. Digital input buffer provides a high-impedance buffer for the external digital input. The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripheral. Enabling the input buffer provides possibility to read the pin state via the CPU. If pin is connected to an analog signal, the input buffer should be disabled to avoid crowbar currents. For more information refer to device TRM and the device datasheet.

Multiple pins on a port can be updated using direct port register writes with an appropriate port mask. An example is shown below, highlighting the different ways of configuring Port 1 pins using:

• Port output data register
• Port output data set register
• Port output data clear register

    GPIO_PRT_Type* portAddr;
    uint8_t value;
    
    /* Set the port address */
    portAddr = GPIO_PRT1;
    
    /* Set the drive mode to STRONG for pins P1[0], P1[2] and P1[3] (other pins in this port are HIGHZ) */
    CY_SET_REG32(&portAddr->CFG, CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE0_Pos | 
                                 CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE2_Pos | 
                                 CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE3_Pos );
    
    /* Set the pins P1[0], P1[2] and P1[3] to high and other pins in this port to low */
    CY_SET_REG32(&portAddr->OUT, GPIO_PRT_OUT_OUT0_Msk | 
                                 GPIO_PRT_OUT_OUT2_Msk | 
                                 GPIO_PRT_OUT_OUT3_Msk);
    
    /* Set the pins P1[2] and P1[3] to low (other pins in this port are unchanged) */
    CY_SET_REG32(&portAddr->OUT_CLR, GPIO_PRT_OUT_CLR_OUT2_Msk | 
                                     GPIO_PRT_OUT_CLR_OUT3_Msk);
    
    /* Set the pin P1[3] to high again (other pins in this port are unchanged) */
    CY_SET_REG32(&portAddr->OUT_SET, GPIO_PRT_OUT_SET_OUT3_Msk);
    
    /* Read the port data (value should be 0b00001001) */
    value = CY_GET_REG32(&portAddr->OUT);

    /* Set pin P1[3] to low (other pins are not impacted) */
    CY_SET_REG32(&portAddr->OUT, _CLR_SET_FLD32U(portAddr->OUT, GPIO_PRT_OUT_OUT3, 0u));
     
    /* Set pin P1[2] to high (other pins are not impacted) */
    CY_SET_REG32(&portAddr->OUT, _CLR_SET_FLD32U(portAddr->OUT, GPIO_PRT_OUT_OUT2, 1u));

More Information

Refer to the technical reference manual (TRM) and the device datasheet.

MISRA-C Compliance

The GPIO driver has the following specific deviations:

MISRA Rule	Rule Class (Required/Advisory)	Rule Description	Description of Deviation(s)
11.4	A	A cast should not be performed between a pointer to object type and a different pointer to object type.	This code is safe because the elements of both GPIO_PRT_V1_Type and GPIO_PRT_V2_Type types have identical alignment.
16.7	A	A pointer parameter in a function prototype should be declared as pointer to const if the pointer is not used to modify the addressed object.	The objects pointed to by the base addresses of the GPIO port are not always modified. While a const qualifier can be used in select scenarios, it brings little benefit in adding this to the affected functions.

Changelog

Version	Changes	Reason for Change
1.20.1	Minor documentation updates.	Documentation enhancement.
1.20	Flattened the organization of the driver source code into the single source directory and the single include directory.	Driver library directory-structure simplification.
	Added the functions for configuring the AMux bus splitter switch cells: Cy_GPIO_SetAmuxSplit Cy_GPIO_GetAmuxSplit	Added a new functionality related to AMux bus.
	Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.	Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.
1.10.1	Updated description for the functions: Cy_GPIO_GetInterruptStatus, Cy_GPIO_GetInterruptMask, Cy_GPIO_GetInterruptStatusMasked. Minor documentation edits.	Documentation update and clarification
1.10	Added input parameter validation to the API functions
1.0	Initial version

API Reference
	Macros
	Functions
	Data Structures
	Enumerated Types