The PSoC 6 I2S Supports the following values for word and channel lengths (with the constraint that word length must be less than or equal to channel length):

• 8 bits
• 16 bits
• 18 bits
• 20 bits
• 24 bits
• 32 bits

The sclk signal is formed by integer division of the input clock source (either internally provided or from the mclk pin). The PSoC 6 I2S supports sclk divider values from 1 to 64.