XMC_ETH_MAC_PORT_CTRL_t Union Reference

#include <xmc_eth_mac.h>

Detailed Description

ETH MAC port control

Field Documentation

__pad0__

uint32_t __pad0__

Reserved bits

__pad1__

uint32_t __pad1__

Reserved bits

clk_rmii

uint32_t clk_rmii

RMII: Continuous 50 MHz reference clock. MII: Receive clock, 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s (::XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t)

clk_tx

uint32_t clk_tx

Transmit clock (only MII), 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s (::XMC_ETH_MAC_PORT_CTRL_CLK_TX_t)

col

uint32_t col

Collision Detect for only MII (::XMC_ETH_MAC_PORT_CTRL_COL_t)

crs

uint32_t crs

Carrier sense for only MII (::XMC_ETH_MAC_PORT_CTRL_CRS_t)

crs_dv

uint32_t crs_dv

RMII: carrier sense/RX_Data valid. MII: RX_Data valid (::XMC_ETH_MAC_PORT_CTRL_CRS_DV_t)

mdio

uint32_t mdio

Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t)

mode

uint32_t mode

RMII or MII (::XMC_ETH_MAC_PORT_CTRL_MODE_t)

rxd0

uint32_t rxd0

Receive data bit 0 (::XMC_ETH_MAC_PORT_CTRL_RXD0_t)

rxd1

uint32_t rxd1

Receive data bit 1 (::XMC_ETH_MAC_PORT_CTRL_RXD1_t)

rxd2

uint32_t rxd2

Receive data bit 2 (only MII) (::XMC_ETH_MAC_PORT_CTRL_RXD2_t)

rxd3

uint32_t rxd3

Receive data bit 3 (only MII) (::XMC_ETH_MAC_PORT_CTRL_RXD3_t)

rxer

uint32_t rxer

Receive error (::XMC_ETH_MAC_PORT_CTRL_RXER_t)

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The documentation for this union was generated from the following file:

• xmc_eth_mac.h