RAM (RAM System Routine)

Error Correction Code (ECC) for RAM. More...

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Detailed Description

Error Correction Code (ECC) for RAM.

The functions and other declarations used in this driver are in cy_ram.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

The PSOC4 HV PA has a volatile static random access memory (SRAM) with Error Correction Code (ECC). The SRAM is used by the processor for storing variables and can program code, which can be written and executed in SRAM. SRAM memory is retained in all power modes (Active, Sleep, and Deep Sleep). At power-up, SRAM is uninitialized and should be written by application code before reading.

ECC Considerations

The ECC engine provides supports for Hamming code with an additional parity bit. This code supports single error correction and double error detection (SECDED). The ECC is applied to the SRAM data and address.

• The ECC corrects single bit errors in SRAM data (stored in SRAM memory).
• The ECC detects single and double bit errors in SRAM data (stored in SRAM memory) and the SRAM address logic. The SRAM stores 40-bit of data:
• a 32-bit data word
• a 7-bit parity
• redundant 1-bit. The 32-bit SRAM data word allows 8-bit, 16-bit, and 32-bit AHB-Lite bus transfers in a single cycle. The 7-bit parity provides error correction and error detection. A 7-bit SECDED parity covers up to 57 data bits, which also provides space for additional 57-32 = 25 data bits. These 25 additional data bits will be used for the SRAM address.

More Information

See the technical reference manual (TRM) for more information about the RAM architecture.

Changelog

Version	Changes	Reason for Change
1.0	Initial version