LTC (Lifetime Counter)

Provides a basic 32-bit lifetime counter with a prescaler (/2 to /32). More...

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	Macros
	Enumerated Types
	Functions

Detailed Description

Provides a basic 32-bit lifetime counter with a prescaler (/2 to /32).

Note

Supported on PSOC4 HVMS/PA.

The functions and other declarations used in this driver are in cy_ltc.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

Provides a basic 32-bit up-counter operation in the DeepSleep domain at a frequency lower than Low-Frequency Clock, which can provide a Deep Sleep interrupt when set by FW (match WAKEUP value) or a regular lifetime counter without an interrupt. With the prescaler, the net resolution of the counter becomes 37-bit causing an overflow every 49.7 days. The counter will continue counting upon overflow.

The lifetime counter shall survive all resets except POR/XRES/BOD.

Clock Source

LTC Solution

The lifetime counter operates on Low-Frequency Clock. The Low-Frequency Clock release depends on the startup time of the clock. Any AHB writes before Low-Frequency Clock is released will be not pass through to the actual lifetime counter configuration until the Low-Frequency Clock starts. If there is a system reset before the synchronization takes place, the values will be reset, and FW will have to write the configuration again. FW can read the counter value to make sure the counter has started.

The lifetime counter includes a prescaler and is triggered from the Low-Frequency Clock clock. The prescaler provides the Low-Frequency Clock from divide-by-2 up to divide-by-32.

The 32-bit counter runs off of the pre-scaled clock. It is capable of wrapping. The initial value is intended to provide a life-cycle count maintained by software. The value is expected to be loaded after POR by software, and software periodically updates flash to the current count.

Application

• a) The customer wants to know how long the battery has been connected (the same battery that powers our part). The lifetime counter and periodic writes are combined to NV memory. The lifetime counter is up to every 49.7 days of the roll over, which is used to calculate the total time the battery is connected.
  
• b) After manufacturing, some devices are frequently put on a ship, and it can take months to arrive at the destination. When they arrive, the battery is expected to be still in the ready state. It would be better to keep track of actual Lifetime in this mode. In that case, we need to keep PILO and Lifetime counter running, disable WDT, CRWDT, and disable Lifetime wake-up.

Power Modes

The "WAKEUP" value is compared against the hardware "COUNT" value. If there is a match, a Deep Sleep interrupt occurs.

User does NOT need to wait for enable synchronization before entering deepsleep. This will occur within one Low-Frequency Clock cycle. But it is recommended to wait for the enabled status ( Cy_LTC_IsEnabled ) before entering Deep Sleep.

Configuration Considerations

Before using the Cy_LTC_SetDivider or Cy_LTC_SetCounterValue function, disable the lifetime counter by the Cy_LTC_Disable function.

FW shall wait for the counter disabled synchronization before re-enabling the lifetime counter to ensure that the synchronization is completed. The user can read Cy_LTC_IsEnabled to check that the lifetime counter is disabled.

Note

The user can change the WAKEUP value without disabling the lifetime counter

For example:

    /* The Watchdog timer should be unlocked before ILO being enabled. */
    Cy_WDT_Unlock();

    /* A Low frequency clock source should be enabled before this driver usage. */
    Cy_SysClk_IloEnable();

    /* Initialize the lifetime counter driver */
    Cy_LTC_Init();

    /* Disable lifetime counter. */
    Cy_LTC_Disable();

    /* Configure custom divider ratio for preselector. */
    Cy_LTC_SetDivider(CY_LTC_PRESEL_DIV_4);

    /* Reset Counter value */
    Cy_LTC_SetCounterValue(0);

    /* Set 1000 ticks */
    Cy_LTC_SetWakeup(1000);

    /* Due to internal synchronization, it takes about one LFCLK cycle
    to update the counters after divider configuration. */
    uint16_t delay = (uint16_t) (1000000UL / Cy_SysClk_ClkLfGetFrequency());
    /* Wait for LTC counter value changing. */
    Cy_SysLib_DelayUs(delay);
    
    /* Enable lifetime counter. */
    Cy_LTC_Enable();

    /* User can update the wakeup value without disabling the lifetime counter. */
    Cy_LTC_SetWakeup(2000);

    /* It is recommended to wait for status enabled before entering deepsleep. */
    while(!Cy_LTC_IsEnabled())
    {
        Cy_SysLib_Delay(1UL);
    }

    /* Put the device into Deep Sleep mode and wait for an interrupt to wake up. */
    Cy_SysPm_CpuEnterDeepSleep();

    /* The wakeup value is compared against the hardware COUNT value.
    If there is a match will deepsleep interrupt occur. */
    

More Information

For more information on the LTC peripheral, refer to the technical reference manual (TRM).

Changelog

Version	Changes	Reason for Change
1.0	Initial version