DW (DataWire) is one of two DMA hardware implementations.

DW is designed for low latency memory to peripheral or peripheral to memory transfers but can also perform memory to memory transfers and peripheral to peripheral transfers.

DMAC (Direct Memory Access Controller) is the second of two DMA hardware implementations. DMAC is designed with high memory bandwidth for large memory to memory transfers but can perform peripheral to memory, memory to peripheral, and peripheral to peripheral transfers.

Which DMA type is used is dependent on the exact hardware and number of DMA channels already in use. This implementation will attempt to use DMAC first for memory to memory transfers and Datawire otherwise but either type may be used.

User-provided data arrays requirements

CM7 cores support Data Cache. Data Cache line is 32 bytes. User needs to make sure that the source and destination buffer pointers points to 32 byte aligned data. User can use CY_ALIGN(32) macro for 32 byte alignment.