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#define | CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk |
| | The I2C master lost arbitration.
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#define | CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk |
| | The I2C master received a NACK.
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#define | CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk |
| | The I2C master received an ACK.
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#define | CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk |
| | The I2C master generated a Stop.
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#define | CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk |
| | The I2C master bus error (detection of unexpected START or STOP condition)
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#define | CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk |
| | The SPI master transfer is complete: all data elements transferred from the TX FIFO and TX shift register.
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