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PSOC E8XXGP Device Support Library
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PSOC E8XXGP Device Support Library
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MSC is the Master Security Controller which helps to protect the transactions initiated on the bus.
MSC is instantiated on non-CPU paths to provide security extension attributes and to add TrustZone-M capability. MSC Driver provides APIs to configure access rights to the given master (a core, DMA, etc) for each Protection Context (provides a more precise way of applying memory restrictions). Maximum of 32 masters are supported. It also provides API to set the active PC.
The functions and other declarations used in this driver are in cy_ms_ctl.h. You can include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL.
You can use this driver to protect the transactions initiated on the bus.
Devices support multiple CPU subsystems, viz. SYSCPUSS (Power Domain 0 powered by a low-power 32-bit Arm® Cortex-M33 (CM33) CPU, which handles security, control, communication) and APPCPUSS (Power Domain 1 powered by an Arm Cortex-M55 (CM55) processor, which supports M-profile vector extension (MVE), Digital Signal Processing (DSP), and Machine Learning (ML) capabilities).
The default MSC configuration is pre-defined and can be found in the architecture TRM. Each subsystem has its own MSC APIs to be used within it.
Following APIs are used for MSC IP in SYSCPUSS
Cy_Ms_Ctl_ConfigBusMaster
Cy_Ms_Ctl_ConfigMscAcgResp
Cy_Ms_Ctl_SetActivePC
Cy_Ms_Ctl_GetActivePC
Cy_Ms_Ctl_SetPcHandler
Cy_Ms_Ctl_GetPcHandler
Following APIs are used for MSC IP in APPCPUSS
Cy_Ms_Ctl_ConfigBusMasterV1
Cy_Ms_Ctl_ConfigMscAcgRespV1
Cy_Ms_Ctl_SetActivePCV1
Cy_Ms_Ctl_GetActivePCV1
For more information on the MSC , refer to the technical reference manual (TRM).
The MSC driver does not have any specific deviations.
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