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#define | L2CAP_MINIMUM_OFFSET 13 /* plus control(2), SDU length(2) */ |
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#define | L2CAP_BLE_CONN_MIN_OFFSET 9 /* HCI type(1), len(2), handle(2), L2CAP len(2) and CID(2) */ |
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#define | L2CAP_DEFAULT_BLE_CB_POOL_ID 0xFF /* Use the default HCI ACL buffer pool */ |
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#define | L2CAP_BLE_COC_SDU_OFFSET |
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#define | L2CAP_BLE_TX_CONG_START_THRESH 3 |
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#define | L2CAP_BLE_TX_CONG_STOP_THRESH 1 |
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#define | L2CAP_BROADCAST_MIN_OFFSET 11 |
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#define | L2CAP_PING_RESULT_OK 0 /* Ping reply received OK */ |
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#define | L2CAP_PING_RESULT_NO_LINK 1 /* Link could not be setup */ |
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#define | L2CAP_PING_RESULT_NO_RESPONSE 2 /* Remote L2CAP did not reply */ |
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#define | L2CAP_DATAWRITE_FAILED FALSE |
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#define | L2CAP_DATAWRITE_SUCCESS TRUE |
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#define | L2CAP_DATAWRITE_CONGESTED 2 |
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#define | L2CAP_PRIORITY_NORMAL 0 |
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#define | L2CAP_PRIORITY_HIGH 1 |
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#define | L2CAP_DIRECTION_IGNORE 0 /* Set ACL priority direction as ignore */ |
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#define | L2CAP_DIRECTION_DATA_SOURCE 1 /* Set ACL priority direction as source */ |
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#define | L2CAP_DIRECTION_DATA_SINK 2 /* Set ACL priority direction as sink */ |
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#define | L2CAP_CHNL_PRIORITY_HIGH 0 |
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#define | L2CAP_CHNL_PRIORITY_MEDIUM 1 |
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#define | L2CAP_CHNL_PRIORITY_LOW 2 |
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#define | L2CAP_CHNL_DATA_RATE_HIGH 3 |
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#define | L2CAP_CHNL_DATA_RATE_MEDIUM 2 |
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#define | L2CAP_CHNL_DATA_RATE_LOW 1 |
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#define | L2CAP_CHNL_DATA_RATE_NO_TRAFFIC 0 |
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#define | L2CAP_FLUSHABLE_MASK 0x0003 |
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#define | L2CAP_FLUSHABLE_CH_BASED 0x0000 |
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#define | L2CAP_FLUSHABLE_PACKET 0x0001 |
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#define | L2CAP_NON_FLUSHABLE_PACKET 0x0002 |
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#define | L2CAP_FLUSH_CHANNELS_ALL 0xffff |
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#define | L2CAP_FLUSH_CHANNELS_GET 0x0000 |
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#define | L2CAP_ROLE_PERIPHERAL HCI_ROLE_PERIPHERAL |
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#define | L2CAP_ROLE_CENTRAL HCI_ROLE_CENTRAL |
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#define | L2CAP_ROLE_ALLOW_SWITCH 0x80 |
| set this bit to allow switch at create conn
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#define | L2CAP_ROLE_DISALLOW_SWITCH 0x40 |
| set this bit to disallow switch at create conn
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#define | L2CAP_ROLE_CHECK_SWITCH 0xC0 |
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#define | L2CAP_FCR_CHAN_OPT_BASIC (1 << L2CAP_FCR_BASIC_MODE) |
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#define | L2CAP_FCR_CHAN_OPT_ERTM (1 << L2CAP_FCR_ERTM_MODE) |
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#define | L2CAP_FCR_CHAN_OPT_STREAM (1 << L2CAP_FCR_STREAM_MODE) |
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#define | L2CAP_FCR_CHAN_OPT_ALL_MASK (L2CAP_FCR_CHAN_OPT_BASIC | L2CAP_FCR_CHAN_OPT_ERTM | L2CAP_FCR_CHAN_OPT_STREAM) |
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#define | L2C_INVALID_PSM(psm) (((psm) & 0x0101) != 0x0001) |
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#define | L2C_IS_VALID_PSM(psm) (((psm) & 0x0101) == 0x0001) |
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#define | MINIMIUM_DYNAMIC_LE_PSM 0x0080 |
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#define | MAXIMUM_LE_PSM 0x00FF |
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#define | L2C_BLE_INVALID_PSM(le_psm) (!(le_psm) || (le_psm) > MAX_LE_PSM) |
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#define | L2C_BLE_IS_VALID_PSM(le_psm) (((le_psm) != 0) && ((le_psm) <= MAX_LE_PSM)) |
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#define | L2CAP_CH_CFG_MASK_MTU 0x0001 |
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#define | L2CAP_CH_CFG_MASK_QOS 0x0002 |
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#define | L2CAP_CH_CFG_MASK_FLUSH_TO 0x0004 |
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#define | L2CAP_CH_CFG_MASK_FCR 0x0008 |
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#define | L2CAP_CH_CFG_MASK_FCS 0x0010 |
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#define | L2CAP_CH_CFG_MASK_EXT_FLOW_SPEC 0x0020 |
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